1. Field of the Invention
The present invention relates to a Standard Delay Format (abbreviated as SDF hereinafter) file, and more particularly, to a method for reducing a SDF file size.
2. Description of Related Art
Along with the continuous development of the semiconductor technology, the Integrated Circuit (abbreviated as IC hereinafter) has become a most important electronic component in various devices. In order to simplify the IC design process, many IC design tools running on computer have been developed to assist the designer to design IC.
FIG. 1 is a flow chart illustrating a typical IC design process. As shown in the diagram, the IC designer first uses a high level language such as Verilog or VHDL to describe functions provided by the IC, and a RTL file 110 is generated after the description is appropriately edited. The RTL file 110 is then fed into a synthesizer 120, and the RTL file 110 is converted into a netlist 140 with the cell level by referring a timing library 130 provided by the semiconductor manufacture. Besides containing the cells which can achieve the IC functions, the netlist 140 further contains an interconnect, which describes the connection between cells, and both of them are used in the IC layout design.
Wherein, in order to simulate the functions of the IC design before manufacturing the IC, a delay calculator 150 shown in the diagram is used to generate a SDF file 170 which is required by a simulator 190 to perform a simulation by referring to the netlist 140 and the timing library 130. The SDF file 170 generally contains the delay time of the transmitted signal for the I/O paths of cells and the connections between cells. Before the layout is completed, the value of the delay time is only estimated. However, after the layout is completed, a RC extraction data 145 generated by a RC extractor is referred to calculate a delay time with more precise value. The RC extraction data 145 is the data associated to the physical resistance and capacitance extracted by the RC extractor. Afterwards, a simulation result is output by the simulator 190 according to the netlist 140, the SDF file 170, mentioned above, and a simulation model 180.
However, for a cell with more than two I/O paths, a cell description in the SDF file 170 also contains a state-dependent description. Since the amount of the state-dependent descriptions grows along with the increase of the number of the cell input terminals. For example, for a cell with two input terminals, the delay data of each I/O path contains two state-dependent descriptions, and for a cell with three input terminals, the delay data of each I/O path contains four state-dependent descriptions, such that the simulator 190 can determine the physical delay time according to the status of the cell input terminals when it is performing the simulation. Accordingly, it is not easy to reduce the size of the SDF file 170.